speculative.qbk 2.3 KB

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  1. [/
  2. Copyright Oliver Kowalke 2017.
  3. Distributed under the Boost Software License, Version 1.0.
  4. (See accompanying file LICENSE_1_0.txt or copy at
  5. http://www.boost.org/LICENSE_1_0.txt
  6. ]
  7. [#speculation]
  8. [section:speculation Specualtive execution]
  9. [heading Hardware transactional memory]
  10. With help of hardware transactional memory multiple logical processors
  11. execute a critical region speculatively, e.g. without explicit
  12. synchronization.[br]
  13. If the transactional execution completes successfully, then all memory
  14. operations performed within the transactional region are commited without any
  15. inter-thread serialization.[br]
  16. When the optimistic execution fails, the processor aborts the transaction and
  17. discards all performed modifications.[br]
  18. In non-transactional code a single lock serializes the access to a critical
  19. region. With a transactional memory, multiple logical processor start a
  20. transaction and update the memory (the data) inside the ciritical region.
  21. Unless some logical processors try to update the same data, the transactions
  22. would always succeed.
  23. [heading Intel Transactional Synchronisation Extensions (TSX)]
  24. TSX is Intel's implementation of hardware transactional memory in modern Intel
  25. processors[footnote intel.com: [@https://software.intel.com/en-us/node/695149
  26. Intel Transactional Synchronization Extensions]].[br]
  27. In TSX the hardware keeps track of which cachelines have been read from and
  28. which have been written to in a transaction. The cache-line size (64-byte) and
  29. the n-way set associative cache determine the maximum size of memory in a
  30. transaction. For instance if a transaction modifies 9 cache-lines at a
  31. processor with a 8-way set associative cache, the transaction will always be
  32. aborted.
  33. [note TXS is enabled if property `htm=tsx` is specified at b2 command-line and
  34. `BOOST_USE_TSX` is applied to the compiler.]
  35. [note A TSX-transaction will be aborted if the floating point state is modified
  36. inside a critical region. As a consequence floating point operations, e.g.
  37. store/load of floating point related registers during a fiber (context) switch
  38. are disabled.]
  39. [important TSX can not be used together with MSVC at this time!]
  40. Boost.Fiber uses TSX-enabled spinlocks to protect critical regions (see section
  41. [link tuning Tuning]).
  42. [endsect]